How to Make 4*8 Decoder in Verilog HDL in FPGA. Data Flow Modeling module decoder_assign(a, y); input [3:0] a; output [7:0] y; assign y = ~a[0] ~a[1] ~a[2] ~a[3]; assign y= a[… Posted on 05 March 2016 at 11:20 by waseem2046 read more