How to Make 4*8 Decoder in Verilog HDL in FPGA.

Posted on at


Data Flow Modeling

module decoder_assign(a, y);

input [3:0] a;

output [7:0] y;

assign y = ~a[0] & ~a[1] & ~a[2] & ~a[3];

assign y= a[0] & ~a[1] & ~a[2] & ~a[3];

assign y = ~a[0] & a[1] & ~a[2] & ~a[3];

assign y = a[0] & a[1] & ~a[2] & ~a[3];

assign y = ~a[0] & ~a[1] & a[2] & ~a[3];

assign y = a[0] & ~a[1] & a[2] & ~a[3];

assign y = ~a[0] & a[1] & a[2] & ~a[3];

assign y = a[0] & a[1] & a[2] & ~a[3];

assign y = ~a[0] & ~a[1] & ~a[2] & a[3];

assign y = a[0] & ~a[1] & ~a[2]  & a[3];

assign y = ~a[0] & a[1] & ~a[2] & a[3];

assign y = a[0] & a[1] & ~a[2]  & a[3];

assign y = ~a[0] & ~a[1] & a[2] & a[3];

assign y = a[0] & ~a[1] & a[2]  & a[3];

assign y = ~a[0] & a[1] & a[2]  & a[3];

assign y = a[0] & a[1] &  a[2]  & a[3];

endmodule


TAGS:


About the author

waseem2046

Subscribe 0
160