Implement a 3X8 Decoder in Verilog using Dataflow modeling.

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//This is the Main code.

 

module decoder(d,x,y,z);

output [7:0] d;

input x,y,z;

assign d[0] = ~x & ~y & ~z;

assign d[1] = ~x & ~y & z;

assign d[2] = ~x & y & ~z;

assign d[3] = ~x & y & z;

assign d[4] =  x & ~y & ~z;

assign d[5] =  x & ~y & z;

assign d[6] =  x & y & ~z;

assign d[7] =  x & y & z;

endmodul

 

 

//This is the Stimulus part.

      module stimulus;

      wire [7:0]d;

      reg x,y,z;

 

      decoder my_decoder(d,x,y,z);

      initial

      begin

      x=0;y=0;z=0;

  #10 x=0; y=0; z=1;

  #10 x=0; y=1; z=0;

  #10 x=0; y=1; z=1;

  #10 x=1; y=0; z=0;

  #10 x=1; y=0; z=1;

  #10 x=1; y=1; z=0;

  #10 x=1; y=1; z=1;

  #10 $stop;

  #10 $finish;

  end

  endmodule

Output 3x8 Decoder:

 

 

 

 

 Implement a 4X16 Decoder using instantiation (Use two 3X8 Decoders):

//This is the Main code.

module decode4_16(d1,d2,x,y,z,w);

output [7:0] d1,d2;

input  x,y,z;

input w;

assign wo=~w;

 

decod3_8 dd1(d1,x,y,z,wo);

decod3_8 dd2(d2,x,y,z,w);

endmodule

 

module decod3_8(d,x,y,z,w1);

output[7:0] d;

input x,y,z;

input w1;

assign d[0] = ~x & ~y & ~z &w1;

assign d[1] = ~x & ~y & z&w1;

assign d[2] = ~x & y &~z&w1;

assign d[3] = ~x & y & z&w1;

assign d[4] =  x & ~y & ~z&w1;

assign d[5] =  x & ~y & z&w1;

assign d[6] =  x & y & ~z&w1;

assign d[7] =  x & y & z&w1;

endmodule

//This is the Stimulus part.

module stimulus;

reg x,y,z;

reg w;

wire [7:0] d1, d2;

 

decode4_16 dd1(d1,d2,x,y,z,w);

initial

 begin

      w=0; x=0;y=0;z=0;

#10 w=0;x=0; y=0; z=1;

#10 w=0;x=0; y=1; z=0;

#10 w=0;x=0; y=1; z=1;

#10 w=0;x=1; y=0; z=0;

#10 w=0;x=1; y=0; z=1;

#10 w=0;x=1; y=1; z=0;

#10 w=0;x=1; y=1; z=1;

#10 w=1;x=0; y=0; z=0;

#10 w=1;x=0; y=0; z=1;

#10 w=1;x=0; y=1; z=0;

#10 w=1;x=0; y=1; z=1;

#10 w=1;x=1; y=0; z=0;

#10 w=1;x=1; y=0; z=1;

#10 w=1;x=1; y=1; z=0;

#10 w=1;x=1; y=1; z=1;

#10 $stop;                   

#10 $finish;

end

endmodule

 Output 4x16 Decoder:

 

 


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